Present invention relates to decoders for memory units and more particularly to decoders for memory units in which the amount and configuration of the storage within the unit can be changed.
In modern data processing systems, memory units are provided with varying amounts of storage. For instance, a memory unit could be built containing 1 to 32 megabytes of storage in units varying in size from one to eight megabytes each. Each unit could be considered a basic storage module (BSM) and each time a BSM is added or subtracted from the meory, the decoding circuit for the addresses supplied to the meory by the processor must be reconfigured. In the past, the reconfiguration of the decorders has generally been performed by rewiring conventional decoder logic in the memory unit. Of course, this involves significant expense and requires tailoring of the decoding circuit to the various combinations of BSM's that may be used. Dynamically reconfigurable decoders have been proposed to eliminate the need for rewiring but up until now the suggested decoders have not been entirely satisfactory because of complexity, limited flexiblity, or cost.